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MSM80C154S image

Número de pieza
MSM80C154SJS

componentes Descripción

Other PDF
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40 Pages

File Size
257 kB

Fabricante
OKI
Oki Electric Industry OKI

GENERAL DESCRIPTION
The MSM80C154S/MSM83C154S, designed for the high speed version of the existing
MSM80C154/MSM83C154, is a higher performance 8-bit microcontroller providing low-power
consumption.
The MSM80C154S/MSM83C154S covers the functions and operating range of the existing
MSM80C154/83C154/80C51F/80C31F.
The MSM80C154S is identical to the MSM83C154S except it does not contain the internal
program memory (ROM).


FEATURES
• Operating range
  Operating frequency : 0 to 3 MHz (Vcc=2.2 to 6.0 V)
                               0 to 12 MHz (Vcc =3.0 to 6.0 V)
                               0 to 24 MHz (Vcc =4.5 to 6.0 V)
  Operating voltage : 2.2 to 6.0 V
  Operating temperature : –40 to +85°C (Operation at +125°C conforms to the other specification.)
• Fully static circuit
• Upward compatible with the MSM80C51F/80C31F
• On-chip program memory : 16K words x 8 bits ROM (MSM83C154S only)
• On-chip data memory : 256 words x 8 bits RAM
• External program memory address space : 64K bytes ROM (Max)
• External data memory address space : 64K bytes RAM
• I/O ports : 4 ports x 8 bits (Port 1, 2, 3, impedance programmable) : 32
• 16-bit timer/counters : 3
• Multifunctional serial port : I/O Expansion mode
                                     : UART mode (featuring error detection)
• 6-source 2-priority level
   Interrupt and multi-level
   Interrupt available by programming IP and IE registers
• Memory-mapped special function registers
• Bit addressable data memory and SFRs
• Minimum instruction cycle : 500 ns @ 24 MHz operation
• Standby functions : Power-down mode (oscillator stop)
                            Activated by software or hardware; providing
                            ports with floating or active status
                            The software power-down stet mode is termi
                            nated by interrupt signal enabling execution from
                            the interrupted address.

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