Description
The MT90221 device is targeted to systems implementing the ATM FORUM UNI specifications for T1/E1 rates or Inverse Multiplexing for ATM (IMA). In the MT90221 architecture, up to 4 physical and independent T1/E1 streams can be terminated through the utilization of off-the-shelf, traditional T1/E1 framers and LIUs. This allows ATM designers to leverage previous T1/E1 design experience, hardware and software implementation, and to select the best T1/E1 framer for the required application.

FEATUREs
• Cost effective, single chip, 4-port ATM IMA and UNI processor
• Up to 4 IMA groups over 4 T1/E1 links can be implemented
• Supports MIXED mode; links not assigned to an IMA group can be used in UNI mode
• Versatile PCM Interface to most popular T1 or E1 framers, reducing development time
• Supports Symmetrical and Asymmetrical Operation
• Supports both Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) clocking modes
• Supports T1 ISDN lines
• Provides UTOPIA Level 2 MPHY Interface (MT90221 device slaved to ATM device)
• Complies with ITU G.804 recommendations for performing cell mapping into T1 and E1 transmission systems
• Provides ATM framing using cell delineation according to the ITU I.432 cell delineation process
• Provides Header Error Control (HEC) verification and generation, error detection, Filler cell filtering (IMA mode) and Idle/ Unassigned cell filtering (UNI mode)
• Provides statistics to support MIB
• Connects to popular asychronous SRAM
• Provides statistics on the number of HEC errors
• 8 bit Microprocessor Interface, compatible with Intel and Motorola
• 3.3V operation / 5V tolerant inputs
• MQFP-208 pin
• JTAG Test support

APPLICATIONs
• Cost effective single chip solution to implement IMA and UNI links over T1 or E1 in all public or private UNI, NNI and B-ICI applications
• ATM Edge switch IMA and UNI Line Card Design
• Can be used for cost reduction in current applications based on FPGA implementation