GENERAL DESCRIPTION
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on the whole chip.

FEATURES
GENERAL
• Single Power Supply Operation
   - 2.7 to 3.6 volt for read, erase, and program operations
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (Dual Output mode) structure
• 512 Equal Sectors with 4K byte each
   - Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each
   - Any Block can be erased individually
• Program Capability
   - Byte base
   - Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V

PERFORMANCE
• High Performance
   - Fast access time: 86MHz serial clock
   - Serial clock of Dual Output mode : 80MHz
   - Fast program time: 0.6ms(typ.) and 3ms(max.)/page
   - Byte program time: 9us (typ.)
   - Fast erase time: 40ms(typ.) /sector ; 0.4s(typ.) /block
• Low Power Consumption
   - Low active read current: 25mA(max.) at 86MHz
   - Low active programming current: 15mA (typ.)
   - Low active sector erase current: 9mA (typ.)
   - Low standby current: 15uA (typ.)
   - Deep power-down mode 2uA (typ.)
• Typical 100,000 erase/program cycles
• 20 years of data retention

SOFTWARE FEATURES
• Input Data Format
   - 1-byte Command code
• Advanced Security Features
   - Block lock protection
      The BP3-BP0 status bit defines the size of the area to be software protection against program and erase instructions
   - Additional 512 bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
   - Automatically erases and verifies data at selected sector
   - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
   - JEDEC 1-byte manufacturer ID and 2-byte device ID
   - RES command for 1-byte Device ID
   - REMS commands for 1-byte manufacturer ID and
   1-byte device ID
• Support Serial Flash Discoverable Parameters (SFDP) mode

HARDWARE FEATURES
• PACKAGE
   - 16-pin SOP (300mil)
   - 8-pin SOP (150mil)
   - 8-pin SOP (200mil)
   - 8-pin PDIP (300mil)
   - 8-land WSON (6x5mm)
   - 8-land USON (4x4mm)
   - 24-Ball BGA
   - All devices are RoHS Compliant and Halogen-free