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MX26L6419TC-10 Hoja de datos - Macronix International

MX26L6419 image

Número de pieza
MX26L6419TC-10

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page
45 Pages

File Size
314.1 kB

Fabricante
MCNIX
Macronix International MCNIX

GENERAL DESCRIPTION
The MXICs MX26L6419 series MTP use the most advance 2 bits/cell Nbit technology, double the storage capacity of memory cell. The device provide the high density MTP memory solution with reliable performance and most cost-effective.
The device organized as by 16 bits of output bus. The device is packaged in 48-Lead TSOP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers.


FEATURES
• 3.0V to 3.6V operation voltage
• Block Structure
    - 64 x 64Kword Erase Blocks
• Fast random / page mode access time
    - 100/25 ns Read Access Time (page depth:8-word)
• 128-bit Protection Register
    - 64-bit Unique Device Identifier
    - 64-bit User Programmable OTP Cells
• 16-Word Write Buffer
    - 14 us/word Effective Programming Time
• Enhanced Data Protection Features Absolute Protection with VPEN = GND
    - Flexible Block Locking
    - Block Erase/Program Lockout during Power Transitions

Performance
• Low power dissipation
    - typical 15mA active current for page mode read
    - 80uA/(max.) standby current
• High Performance
    - Block erase time: 2s typ.
    - Word programming time: 210us typ.
    - Block programming time: 0.8s typ. (using Write to Buffer Command)
• Program/Erase Endurance cycles: 100 cycles

Software Feature
• Support Common Flash Interface (CFI)
    - MTP device parameters stored on the device and provide the host system to access.

Hardware Feature
• ACC pin
    - 12V VPP for fast program/erase mode.
• VPEN pin
    - For Erase /Program/ Block Lock enable.
• VCCQ Pin
    - The output buffer power supply, control the device s output voltage.
• RESET pin
    - Hardware reset

Packaging
    - 48-Lead TSOP

Technology
    - Two bits per cell Nbit (0.25u) MTP Technology

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

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