Introduction
The decreasing size of features on integrated circuits (45 nm and smaller) is driving the need for new parametric test capabilities. These capabilities must accommodate the advanced test structures developed for fast yield ramp up in process integration as well as process monitoring in semiconductor manufacturing.

High-throughput measurement of high volume parametric data is required to shorten the time for ramping up the process yield. This is accomplished by statistically analyzing and correcting the cause of wide range of process performance variations across a 300 mm wafer. Advanced test structures, addressable array test structures that contain address decoder circuitry, and a large number of test array elements with fewer probing pads and silicon area have been developed by major semiconductor manufacturers for this purpose.