[Performance-Semiconductor]

DESCRIPTION
The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs and outputs are fully TTL-compatible. The RAM operates from a single 5V ± 10% tolerance power supply.

FEATURES
■ Full CMOS, 6T Cell
■ High Speed (Equal Access and Cycle Times)
   – 10/12/15/20/25 ns (Commercial)
   – 15/20/25/35 ns (Military)
■ Chip Clear Function
■ Low Power Operation
   – 713 mW Active –10 ns (Commercial)
   – 550 mW Active –25 ns (Commercial)
■ Single 5V ± 10% Power Supply
■ Separate Input and Output Ports
■ Three-State Outputs
■ Fully TTL Compatible Inputs and Outputs
■ Standard Pinout (JEDEC Approved)
   – 24-Pin 300 mil DIP
   – 24-Pin 300 mil SOIC
   – 28-Pin LCC (350 x 550 mils)
   – 24-Pin CERPACK