Description
The PI90LV14 implements low voltage differential signaling (LVDS) to achieve clocking rates as high as 320MHz with low skew.
The PI90LV14 is a low-skew 1:5 clock distribution chip which incorporates multiplexed clock inputs to allow for distribution of a lower-speed, single-ended clock or a high-speed system clock. When LOWthe SEL pin will select the differential clock input.

FEATUREs
• Meets and Exceeds the Requirements of ANSI TIA/EIA-644-1995
• Designed for clocking rates up to 320MHz
• Operates from a single 3.3V Supply
• Low Voltage Differential Signaling (LVDS) with Output Voltages of ±350mV into a 100Ωload
• Choice between LVDS or TTL clock input
• Synchronous Enable/Disable
• Clock outputs default LOW when inputs open
• Multiplexed clock input
    - Internal 300kΩpullup resistor on input pins
    - CLK and CLK have 110Ωinternal termination (PI90LVT14)
• 50ps Output-to-Output Skew
• 475ps typical propagation delay
• Bus Pins are high impedance when disabled or with VCC less than 1.5V
• TTL inputs are 5V Tolerant
• Power Dissipation at 400Mbits/s of 150mW
• Function compatible to Motorola (PECL)
    MC100EL14 and Micrel/Synergy (PECL)
    SY100EL14V
• >9kV ESD Protection
• 20-pin TSSOP (L) and QSOP (Q) packages