INTRODUCTION
Unless specifically noted, all references to the 80C186XL apply to the 80C188XL. References to
pins that differ between the 80C186XL and the 80C188XL are given in parentheses.
The following Functional Description describes the base architecture of the 80C186XL. The 80C186XL is a very high integration 16-bit microprocessor. It combines 15± 20 of the most common microproces sor system components onto one chip. The 80C186XL is object code compatible with the 8086/8088 microprocessors and adds 10 new in struction types to the 8086/8088 instruction set.

Low Power, Fully Static Versions of 80C186/80C188
Operation Modes:
  Enhanced Mode
   DRAM Refresh Control Unit
   Power-Save Mode
   Direct Interface to 80C187 (80C186XL Only)
  Compatible Mode
   NMOS 80186/80188 Pin-for-Pin Replacement for Non-Numerics Applications
Integrated Feature Set
 Static, Modular CPU
 Clock Generator
 2 Independent DMA Channels
 Programmable Interrupt Controller
 3 Programmable 16-Bit Timers
 Dynamic RAM Refresh Control Unit
 Programmable Memory and Peripheral Chip Select Logic
 Programmable Wait State Generator
 Local Bus Controller
 Power-Save Mode
 System-Level Testing Support (High Impedance Test Mode)
Completely Object Code Compatible with Existing 8086/8088 Software and Has 10 Additional Instructions over 8086/8088
Speed Versions Available
 25 MHz (80C186XL25/80C188XL25)
 20 MHz (80C186XL20/80C188XL20)
 12 MHz (80C186XL12/80C188XL12)
Direct Addressing Capability to 1 MByte Memory and 64 Kbyte I/O
Available in 68-Pin:
 Plastic Leaded Chip Carrier (PLCC)
 Ceramic Pin Grid Array (PGA)
 Ceramic Leadless Chip Carrier (JEDEC A Package)
Available in 80-Pin:
 Quad Flat Pack (EIAJ)
 Shrink Quad Flat Pack (SGFP)
Available in Extended Temperature Range (b40§Ctoa85§C)