ARCHITECTURAL OVERVIEW
The S3C24A0A is a 16/32-bit RISC microprocessor, designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W performance for the 2.5G & 3G communication services, the S3C24A0A adopts dual-32-bit bus architecture and includes many powerful hardware accelerators for the motion video processing, serial communications, and etc. For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated.

FEATURES
This section will explain the features of the S3C24A0A. Figure 1-1 is an overall block diagram of the S3C24A0A.

MICROPROCESSOR AND OVERALL ARCHITECTURE
• SoC (System-on-Chip) for mobile phones and general embedded applications.
• 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ-S CPU core.
• ARM’s Jazelle Java technology enhanced ARM architecture MMU to support WinCE, Symbian and Linux
• Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance
• 4 way set-associative cache with I-Cache (16KB) and D-Cache (16KB).
• 8-words per line with one valid bit and two dirty bits per line
• Pseudo random or round robin replacement algorithm.
• Write through or write back cache operation to update the main memory.
• The write buffer can hold 16 words of data and four addresses.
• ARM926EJ-S core supports the ARM debug architecture
• Internal AMBA (Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB)
• Dual AHB bus for high-performance processing (AHB-I & AHB-S)

MEMORY SUBSYSTEM
• High bandwidth Memory subsystem with two access channels (accesses from two AHB buses) and three-channel memory ports
• Double the bandwidth with the simultaneous access capability
• ROM/SRAM/NOR-Flash/NAND-Flash channel
• One SDRAM channels
• Up to 1GB Address space
• Low-power SDRAM interface support : Mobile SDRAM function
   – DS: Driver Strength Control
   – TCSR: Temperature Compensated Self-Refresh Control
   – PASR: Partial Array Self-Refresh Control
• NAND Flash Boot Loader with the ECC circuitry to support booting from NAND Flash
   – 4KB Stepping Stone
   – Support 1G, 2G bit NAND Flash