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SK70708PE Hoja de datos - Intel

SK70704 image

Número de pieza
SK70708PE

componentes Descripción

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54 Pages

File Size
498 kB

Fabricante
Intel
Intel Intel

The HDSL Data Pump is a chip set consisting of the following two devices:
■ SK70704 Analog Core Chip (ACC)
■ SK70707 (68-pin PLCC) or SK70708 (44-pin PLCC) HDSL Digital Transceiver (HDX)

The HDSL Data Pump is a 2-wire transceiver which provides echo-cancelling and 2B1Q line coding. It incorporates transmit pulse shaping, filtering, line drivers, receive equalization, timing and data recovery to provide 1168 kbps, clear-channel, “data pipe” transmission. The Data Pump provides Near-End Cross-Talk (NEXT) performance in excess of that required over all ETSI test loops. Typical transmission range on 0.4 mm cable exceeds 3.6 km in a noise-free environment or 2.8 km with a 0 dB margin over 10 µV/√Hz ETSI noise.
The Data Pump meets the requirements of ETSI ETR-152. It provides one end of a single-channel HDSL transmission system from the twisted pair interface back to the Data Pump/HDSL data interface. The Data Pump can be used at either the NTU or the LTU end of the interface.

Product Features
■ Fully integrated, 2-chip set for interfacing to 2-wire HDSL lines at 1168 kbps
■ Single +5 V supply
■ Integrated line drivers, filters and hybrid circuits result in greatly reduced external logic and simplified support circuitry requirements
■ Simple line interface circuitry, via transformer coupling, to twisted pair line
■ Internal ACC voltage reference
■ Integrated VCO circuitry
■ Converts serial binary data to scrambled 2B1Q encoded data
■ Self-contained activation/start-up state machine for simplified single loop designs
■ Programmable for either line termination (LTU) or network termination (NTU) applications
■ Compliant with ETSI ETR-152 (1995)
■ Compliant with ITU G.991.1
■ Design allows for operation in either Software Control or stand alone Hardware Control mode
■ Typical power consumption less than 1.2 W allowing remote power feeding for repeater and NTU equipment
■ Input or Output Reference Clock of 18.688 MHz
■ Digital representation of receive signal level and noise margin values available for SNR controlled activation


APPLICATIONs
■ E1 (2-pair) and fractional E1 transport
■ N-channel digital pair-gain
■ Wireless base station to switch interface
■ Campus and private networking
■ High-Speed digital modems

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