These8-bit shift registers have multiplexed input/output data ports to accomplishfull 8-bit datahandling in a single 20-pin package. Serial data may enterthe shift-right register througheither D0 or D1 inputs as selected by the dataselect pin. A serial output is also provided. Synchronous parallel loading isachieved by taking the register enable and the S/Pinputs low. This places thethree-state input/output ports in the data input mode. Data is entered on the low-to-high clock transition.Thedata extend function repeats the sign in theQAflip-flopduring shifting. An overriding clear input clears the internal registerswhen taken low whether the outputs are enabled or off. The output enable does not affect synchronous operation of the register.

• Multiplexed Inputs/Outputs Provide Improved Bit Density
• Sign Extend Function
• Direct Overriding Clear
• 3-State Outputs Drive Bus Lines Directly