GENERAL DESCRIPTION
The TZA3005 SDH/SONET transceiver chip is a fully integrated serialization/deserialization SDH/SONET STM4/OC12 (622.08 Mbits/s) and STM1/OC3 (155.52 Mbits/s) interface device. It performs all necessary serial-to-parallel and parallel-to-serial functions in accordance with SDH/SONET transmission standards. It is suitable for SONET-based applications and can be used in conjunction with the TZA3004 clock recovery device, the TZA3000 optical receiver and the TZA3001 laser driver. Figure 13 shows a typical network application.
A high-frequency phase-locked loop is used for on-chip clock synthesis, which means a slower external transmit reference clock can be used. A 19.44, 38.88, 51.84 or 77.76 MHz reference clock can be used, in support of existing system clocking schemes. The TZA3005 performs SDH/SONET frame detection.
The low jitter PECL interface ensures that Bellcore, ANSI, and ITU-T bit-error rate requirements are satisfied. The TZA3005 comes in a compact QFP64 package.

FEATURES
• Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s)
• Supports 19.44, 38.88, 51.84 and 77.76 MHz reference clock frequencies
• Meets Bellcore, ANSI and ITU-T specifications
• Integral high-frequency PLL for clock generation
• Interface to TTL logic
• Low jitter PECL (Positive Emitter Coupled Logic) interface.
• 4- or 8-bit STM1/OC3 TTL/CMOS data path
• 4- or 8-bit STM4/OC12 TTL/CMOS data path
• No external filter components required
• QFP64 package
• Diagnostic and line loopback modes
• Lock detect
• LOS (Loss of Signal) input
• Low power (900 mW typically)

APPLICATIONS
• SDH/SONET modules
• SDH/SONET-based transmission systems
• SDH/SONET test equipment
• ATM over SDH/SONET
• Add drop multiplexers
• Broadband cross-connects
• Section repeaters
• Fiber optic test equipment.
• Fiber optic terminators