General Description
The VSC6108/10/12 are a family of low-jitter clock multiplication and distribution ICs. Each IC uses a phase locked-loop to lock an on-chip low-noise VCO to an off-chip reference frequency. The VCO output can be divided down and is output to 18 differential ECL outputs. The VSC6108/10/12 are packaged in a 10 mm x 10 mm 64-pin plastic quad flat pack and consume less than 2 Watts from a single 3.3V power supply.

FEATUREs
• Recommended Companion for VSC6250 500MHz Deskew IC and Vitesse Timing Generator ICs
• Input Clock Frequency: 50MHz to 622MHz
• Output Clock Frequency: 100MHz to 1.25GHz
• 1 Differential ECL or PECL Clock Input
• 18 Differential ECL or PECL Clock Outputs
• Very Low Jitter: 4ps rms, 25ps Peak-to-Peak
• 10µs Lock Time
• < 50ps Skew Between Outputs
• Single Supply: 3.3V + 5% @ 2 Watts
• Commercial (0o to +70oC) Temperature Range
• Package: 10mm x 10mm 64 PQFP