FEATURES
■ Access Times of 50*, 60, 70, 90, 120, 150ns
■ Packaging:
   • 66 pin, PGA Type, 1.075 inch square, Hermetic Ceramic HIP (Package 400)
   • 68 lead, Hermetic CQFP (G2U)1, 22.4mm (0.880 inch) square, 3.56mm (0.140 inch) high (Package 510)
   • 68 lead, Hermetic CQFP (G1U), 23.9mm (0.940 inch) square, 3.56mm (0.140 inch) high (Package 519)
   • 68 lead, Hermetic CQFP (G1T), 23.9mm (0.940 inch) square, 4.06mm (0.160 inch) high (Package 524)
■ Sector Architecture
   • 8 equal size sectors of 16KBytes each
   • Any combination of sectors can be concurrently erased. Also supports full chip erase
■ 100,000 Erase/Program Cycles Typical, 0°C to +70°C
■ Organized as 128Kx32
■ Commercial, Industrial and Military Temperature Ranges
■ 5 Volt Programming. 5V ± 10% Supply
■ Low Power CMOS, 1mA Standby Typical
■ Embedded Erase and Program Algorithms
■ TTL Compatible Inputs and CMOS Outputs
■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation
■ Page Program Operation and Internal Program Control Time
■ Weight
   WF128K32-XG1UX5 - 5 grams typical
   WF128K32-XG1TX5 - 5 grams typical
   WF128K32-XG2UX51 - 8 grams typical
   WF128K32-XH1X5 - 13 grams typical