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A8251

Programmable Communications Interface

Altera Corporation 

a8251 Programmable Communications Interface Data Sheet

Table 10. a8251 Programming Sequence

cnd nrd nwr ncs

Operation

Comment

1

1

0

0 Microprocessor writes to the MIR. Must occur immediately following a total

state reset or internal state reset.

1

1

0

0 Microprocessor writes the first sync Skipped in asynchronous operation.

character.

1

1

0

0 Microprocessor writes the second Skipped in asynchronous operation or if

sync character.

bit 7 of the MIR (synchronous operation)

is set to a logic high.

1

1

0

0 Microprocessor writes to the

command instruction register.

Random access.

0

1

0

0 Microprocessor writes to the TBR. Random access.

1

0

1

0 Microprocessor reads the status

Random access.

register.

0

0

1

0 Microprocessor reads the RBR.

Random access.

Receiver Operation (Asynchronous)

When the a8251 is programmed for asynchronous operation, the receiver

includes the following functions:

s Start bit detection

s Data bit sampling

s Parity/stop bit detection

s Error detection

s Receiver buffer register transfer

s Break detection

Start Bit Detection

The a8251 begins receiving data when a start bit is detected. A start bit is

a logic low on the rxd input, which is sampled on each rising clock edge

of the nrxc signal. Once the a8251 detects a logic low, it begins counting

the number of logic low samples according to the specified divide-by

mode.

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