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A8251

Programmable Communications Interface

Altera Corporation 

a8251 Programmable Communications Interface Data Sheet

Figure 10 shows the read and write data cycles for the a8251.

Figure 10. Read & Write Data Cycles

The X indicates “don’t care.”

Read Data

rxrdy

nrd

din

cnd

X

ncs

Valid Data

X

Write Data

txrdy

nwr

din

X

cnd

X

ncs

Valid Data

X

X

Variations &

Clarifications

The following characteristics distinguish the Altera® a8251 from the

Intel 8251A device:

s The a8251 has separate input and output data buses, while the

Intel 8251A device has a bidirectional data bus.

s The a8251 has separate extsyncd and syn_brk signals, while the

Intel 8251A device has a bidirectional SYNDET/BRKDET signal.

s In a write cycle to the a8251, the din[7..0] inputs must be held for

one ntxc clock cycle after the rising edge of the nwr signal.

s The a8251 has an active low reset input. The Intel 8251A has an

active-high reset input.

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Altera Corporation

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