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A8251

Programmable Communications Interface

Altera Corporation 

a8251 Programmable Communications Interface Data Sheet

Error Detection

Three errors can occur when the a8251 is receiving: framing, overrun,

and parity. Refer to Table 9 on page 33 of this data sheet for error

definitions.

Receiver Buffer Register Transfer

Once the last stop bit is received, or a framing error is detected, the data

in the shift register is transferred to the RBR. At this point, all status bits

associated with this data word are set, including the rxrdy bit. The

receiver process concludes when the microprocessor reads data from the

RBR.

Break Detection

In asynchronous operation, the syn_brk signal indicates that the receiver

has detected a break condition. A break condition is defined as the

condition when the rxd signal is continuously low, i.e., for an entire

character sequence including start, stop, and parity bits. The syn_brk bit

can be reset by a total state reset operation or by the rxd signal returning

to a logic high. See Figure 4.

Figure 4. Receiver Control & Error Signals (Asynchronous)

The X indicates “don’t care.”

syn_brk

fe

oe

Second Data Bit Lost

rxrdy

cnd

X

X

nwr

X

X

X

nrd

rxd

First

Data Bit

Second

Data Bit

Third

Data Bit

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