XR16C864CQ(2004) Ver la hoja de datos (PDF) - Exar Corporation

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XR16C864CQ
(Rev.:2004)

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

Exar Corporation 

XR16C864

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0.1

inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the TX FIFO and TSR are

reported in the Line Status Register (LSR bit-5 and bit-6).

2.12.1 Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

2.12.2 Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

FIGURE 6. TRANSMITTER OPERATION IN NON-FIFO MODE

Data

Byte

T rans m it

Holding

Register

(THR)

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

16X

Clock

Transmit Shift Register (TSR)

M

L

S

S

B

B

TXNOFIFO1

2.12.3 Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the TX FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when

the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set

when TSR/TX FIFO becomes empty.

FIGURE 7. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

Data Byte

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.

Auto Software Flow Control

RX FIFO

THR

THR Interrupt (ISR bit-1) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

16X Clock

Transmit Data Shift Register

(TSR)

TXFIFO1

14

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