XR16C864CQ(2004) Ver la hoja de datos (PDF) - Exar Corporation

Número de pieza

componentes Descripción

Lista de partido

XR16C864CQ
(Rev.:2004)

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

Exar Corporation 

XR16C864

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0.1

Pin Description

NAME

100-QFP

TYPE

PIN #

DESCRIPTION

CSD#

(N.C.)

68

I When 16/68# pin is at logic 1, this input is chip select D (active low) to enable channel D

in the device.

When 16/68# pin is at logic 0, this input is not used.

INTA

(IRQ#)

12

O When 16/68# pin is at logic 1 for Intel bus interface, this ouput becomes channel A inter-

(OD) rupt output. The output state is defined by the user and through the software setting of

MCR[3]. INTA is set to the active mode when MCR[3] is set to a logic 1. INTA is set to the

three state mode when MCR[3] is set to a logic 0 (default). See MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, this output becomes device inter-

rupt output (active low, open drain). An external pull-up resistor is required for proper

operation.

INTB

INTC

INTD

(N.C.)

18

O When 16/68# pin is at logic 1 for Intel bus interface, these ouputs become the interrupt

63

outputs for channels B, C, and D. The output state is defined by the user through the soft-

69

ware setting of MCR[3]. The interrupt outputs are set to the active mode when MCR[3] is

set to a logic 1 and are set to the three state mode when MCR[3] is set to a logic 0

(default). See MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, these outputs are unused and

will stay at logic zero level. Leave these outputs unconnected.

INTSEL

87

TXRDYA#

5

TXRDYB#

25

TXRDYC#

56

TXRDYD#

81

I Interrupt Select (active high, input with internal pull-down).

When 16/68# pin is at logic 1 for Intel bus interface, this pin can be used in conjunction

with MCR bit-3 to enable or disable the INT A-D pins or override MCR bit-3 and enable

the interrupt outputs. Interrupt outputs are enabled continuously by making this pin a

logic 1. Making this pin a logic 0 allows MCR bit-3 to enable and disable the interrupt out-

put pins. In this mode, MCR bit-3 is set to a logic 1 to enable the continuous output. See

MCR bit-3 description for full detail. This pin must be at logic 0 in the Motorola bus inter-

face mode.

O UART channels A-D Transmitter Ready (active low). These outputs provide the TX FIFO/

THR status for transmit channels A-D. See Table 5. If Direct Memory Access is enabled,

these outputs become Transmit Direct Memory Access Request outputs. See TXDRQ pin

description for more details. If these outputs are unused, leave them unconnected.

RXRDYA# 100

RXRDYB#

31

RXRDYC#

50

RXRDYD#

82

O UART channels A-D Receiver Ready (active low). These outputs provide the RX FIFO/

RHR status for receive channels A-D. See Table 5. If Direct Memory Access is enabled,

these outputs become Receive Direct Memory Access Request outputs. See RXDRQ pin

description for more details. If these outputs are unused, leave them unconnected.

TXRDY#

45

O Transmitter Ready (active low). This output is a logically wire-ORed status of TXRDY#

A-D. See Table 5. If this output is unused, leave it unconnected.

RXRDY#

44

O Receiver Ready (active low). This output is a logically wire-ORed status of RXRDY# A-D.

See Table 5. If this output is unused, leave it unconnected.

FSRS#

76

I FIFO Status Register Select (active low input with internal pull-up).

The content of the FSTAT register is placed on the data bus when this pin becomes

active. However it should be noted, D0-D3 contain the inverted logic states of TXRDY#

A-D pins, and D4-D7 the logic states (un-inverted) of RXRDY# A-D pins. Address line is

not required when reading this status register.

DIRECT MEMORY ACCESS INTERFACE

4

Share Link: