HS-82C85RH(2000) Ver la hoja de datos (PDF) - Intersil
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HS-82C85RH Datasheet PDF : 16 Pages
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HS-82C85RH
Oscillator/Clock Start Control
Once the oscillator is stopped (or committed to stop) or at
power-on, the restart sequence is initiated by a HIGH state
on START or LOW state on RES. If F/C is HIGH, then restart
occurs immediately after the START or RES input is
synchronized internally. This insures that stopped outputs
(CLK, PCLK, OSC and CLK50) start cleanly with the proper
phase relationship.
If F/C is low (crystal oscillator mode), a HIGH state on the
START input or a low state on RES causes the crystal
oscillator to be restarted. The stopped outputs remain
stopped, until the oscillator signal amplitude reaches the X1
Schmitt trigger input threshold voltage and 8192 cycles of
the crystal oscillator output are counted by an internal
counter. After this count is complete, the stopped outputs
(CLK, CLK50, PCLK) start cleanly with the proper phase
relationships.
Typically, any input signal which meets the START input
timing requirements can be used to start the HS-82C85RH.
In many cases, this would be the INT output from an
HS-82C59A CMOS Priority Interrupt Controller (see Figure
16). This output, which is active high, can be connected to
both the HS-82C85RH START pin and to the INTR input on
the microprocessor.
When the INT output becomes active (as a result of a
“restart” IRQ or a system reset), the oscillator/clock circuit on
the HS-82C85RH will restart. Upon completion of the
appropriate restart sequence, the CLK signal to the CPU will
become active. The CPU can then respond to the still-
pending interrupt request.
Oscillator/Clock Stop Control
The S0, S1, and S2/STOP control lines determine when the
HS-82C85RH clock outputs or oscillator will stop. These
three lines are designed to connect directly to the MAXimum
mode HS-80C86RH status lines as shown in Figure 17.
When used in this configuration, the HS-82C85RH will
automatically recognize a software HALT command from the
HS-80C86RH and stop the system clocks or oscillator. This
allows complete software control of the STOP function.
If the HS-80C86RH is used in the MINimum mode, the
HS-82C85RH can be controlled using the S2/STOP input
(with S0 and S1 held high). This can be done using the
circuit shown in Figure 18. Since the HS-80C86RH, when
executing a halt instruction in minimum mode, issues a
single ALE pulse with no corresponding bus signals (DEN
remains high), the ALE pulse will be clocked through the
74HC74 and put the HS-82C85RH into stop mode.
HS-82C59A
INT
HS-82C85RH
START
CLK
HS-80C86RH
INTR
CLK
FIGURE 16. START CONTROL USING HS-82C59ARH
INTERRUPT CONTROLLER
S2
S2/STOP
S1
S1
S0
S0
MIN/MAX
HS-80C86RH
HS-82C85RH
FIGURE 17. STOP CONTROL USING HS-80C86RH MAXIMUM
MODE STATUS LINES
HS-80C86RH
MICROPROCESSOR
ALE
DEN
RESET
MIN/MAX
VDD
74HC74 QUAD D FLIP-FLOP WITH CLEAR
1D 1Q
2D 2Q
CLR
3D 3Q
4D
4Q
CLK
TO HS-80C86RH
AND PERIPHERALS
VDD
HS-82C85RH
CLOCK CONTROLLER/
GENERATOR
S0
S1
S2/STOP
CLK
RESET
FIGURE 18. STOP CONTROL USING HS-80C86RH IN MINIMUM MODE
12
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