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HS-82C85RH
(Rev.:2000)

Radiation Hardened CMOS Static Clock Controller/Generator

Intersil 

HS-82C85RH

The HS-82C85RH status inputs S2/STOP, S1, S0 are

sampled on the rising edge of CLK. The oscillator (F/C LOW

only) and clock outputs are stopped by S2/STOP, S1, S0

being in the LHH state on a low-to-high transition of CLK. This

LHH state must follow a passive HHH state occurring on the

previous low-to-high CLK transition. CLK and CLK50 will stop

in the logic HIGH state after two additional complete cycles of

CLK. PCLK stops in its current state (HIGH or LOW). This is

true for both SLOW and FAST mode operation.

Stop-Oscillator Mode

When the HS-82C85RH is stopped while in the crystal mode

(F/C LOW), the oscillator, in addition to all system clock signals

(CLK, CLK50 and PCLK), are stopped. CLK and CLK50 stop in

the high state. PCLK stops in its current state (high or low).

With the oscillator stopped, HS-82C85RH power drops to its

lowest level. All clocks and oscillators are stopped. All

devices in the system which are driven by the HS-82C85RH

go into the lowest power standby mode. The HS-82C85RH

also goes into standby and requires a power supply current

of less than 100mA.

Stop-Clock Mode

When the HS-82C85RH is in the EFI mode (F/C HIGH) and

a STOP command is issued, all system clock signals (CLK,

CLK50 and PCLK) are stopped. CLK and CLK50 stop in the

high state. PCLK stops in its current state (high or low).

The HS-82C85RH can also provide its own EFI source

simply by connecting the OSC output to the EFI input and

pulling the F/C input HIGH. This puts the HS-82C85RH into

the External Frequency Mode using its own oscillator as an

external source signal (see Figure 19). In this configuration,

when the HS-82C85RH is stopped in the EFI mode, the

oscillator continues to run. Only the clocks to the CPU and

peripherals (CLK, CLK50 and PCLK) are stopped.

Clock Slow/Fast Operation

The SLO/FST input determines whether the CLK and CLK50

outputs run at full speed (crystal or EFI frequency divided by 3)

or at slow speed (crystal or EFI frequency divided by 768) (see

Figure 20). When in the SLOW mode, HS-82C85RH stop-clock

and stop-oscillator functions operate in the same manner as in

the FAST mode, and the frequency of PCLK is unaffected.

X1

X2

EFI

VDD

F/C

OSC

STOP

CONTROL

S2/STOP

S1

S0

START

START

CONTROL

FIGURE 19. STOP-CLOCK MODE IN EFI MODE WITH

OSCILLATOR AS FREQUENCY SOURCE

The SLOW mode allows the CPU and the system to operate

at a reduced rate which, in turn, reduces system power. For

example, the operating power for the HS-80C86RH CPU is

10mA/MHz of clock frequency. When the SLOW mode is

used in a typical 5MHz system, CLK and CLK50 run at

approximately 20kHz. At this reduced frequency, the

average operating current of the CPU drops to 200mA.

Adding the HS-80C86RH 500mA standby current brings the

total current to 700mA.

While the CPU and peripherals run slower and the

HS-82C85RH CLK and CLK50 outputs switch at a reduced

frequency, the main HS-82C85RH oscillator is still running at

the maximum frequency (determined by the crystal or EFI

input frequency.) Since CMOS power is directly related to

operating frequency, HS-82C85RH power supply current will

typically be reduced by 25% - 35%.

EFI OR OSC

PCLK

SLO/FST

CLK

CLK50

FIGURE 20. SLOW/FAST TIMING OVERVIEW

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