MX98726EC Ver la hoja de datos (PDF) - Macronix International
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MX98726EC Datasheet PDF : 56 Pages
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2.1 Pin Description :
PIN# Pin Name
82
CLKIN
49-54, AD[7:0]
59-62, AD[15:8]
76
ALE
70
A19(RXC)
71
A18(RXDV)
72
A17(CRS)
73
A16(COL)
79
RDB
78
WRB
81
INTB
75
BHEB
80
SRDY
47
CSB
48
MIO
P/N:PM0729
MX98726EC
Type
I, TTL
I/O, 4ma
56,57
I/O, 4ma
66-69
I,TTL
I, TTL
I,TTL
I,TTL
I,TTL
I, TTL
I, TTL
O/D, 4ma
I,TTL
O, 4ma
I, TTL
I, TTL
Description
Host Clock Input : 8M to 40 Mhz.
Multiplexed Address/Data Bit [7:0] : Internal pull-down
Multiplexed Address/Data Bit [15:8] : Internal pull-down
Address Latch Enable : Active high
Host Bus Address Bit19, when on-chip tranceiver is used,it is used in
A[19:16], when in MII mode, it is defined as receive clock RXC (25MHz or
2.5MHz) When this pin is used as address bit, it is internally grounded until
Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address
bit. Internal pull-up
Host Bus Address Bit18, when on-chip tranceiver is used,it is used in
A[19:16], when in MII mode, it is defined as receive data valid RXDV
signal. When this pin is used as address bit, it is internally grounded until
Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address
bit. Internal pull-up.
Host Bus Address Bit17, when on-chip tranceiver is used, it is used in
A[19:16], when in MII mode, it is defined as carrier same CRS signal.
When this pin isused as address bit, it is internally grounded until Reg50.6
(A19A16EN bit) is set to enable decoding of this pin as address bit. Inter-
nal pull-up.
Host Bus Address Bit16, when on-chip tranceiver is used, it is used in
A[19:16], when in MII mode, it is defined as collision COL signal. When
this pin is used as address bit, it is internally grounded until Reg50.6
(A19A16EN bit) is set to enable decoding of this pin as address bit. Inter-
nal pull-up.
Host Read Strobe: Active low. Internal pull-up
Host Write Strobe : Active low. Internal pull-up
Host Interrupt Output : Polarity can be programmed, default is active low.
For active Low interrupt application, external pull-up is reguired. For active
high interrupt application, external pull-down is required.
Host Byte High Enable : Internal pull-up.
BHEB A0 Function
0
0
Word Transfer
0
1
Upper Byte Transfer
1
0
Lower Byte Transfer
1
1
Lower Byte Transfer
Synchronous Host Ready Output : Active high synchronized to CLKIN to
indicate data is ready to be transferred. Initially low at the beginning of a
host cycle.
Chip Select : Active low, used to enable GMAC to decode host address.
When high, no host cycle is recognized by MAC.
Host Memory/IO cycle indicator : Set for memory access and reset for IO
access. Internal pull-up. Decode of MIO can be disable by DISMIO regis-
ter bit. Default is enabled.
REV. 1.1, MAY. 28, 2001
5
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