MX98726EC Ver la hoja de datos (PDF) - Macronix International
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MX98726EC Datasheet PDF : 56 Pages
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MX98726EC
10/100 Tranceiver interface :
PIN#
14
17
16
23
24
29
Pin Name
RDA
CKREF(X1)
X2
RXIN
RXIP
TXON
Type
O
I, TTL
O
I
I
O
30
TXOP
O
32
CPK
O
33
RTX2EQ
O
34
RTX
O
Miscellaneous :
Description
RDA external resistor to ground: 10K ohm, 5%
25Mhz , 30 PPM external osc./crystal input :
25Mhz , 30 PPM external crystal output :
Twisted pair receive differential input: support both 10/100 Mbps speed
Twisted pair receive differential input: support both 10/100 Mbps speed
Twisted pair transmit differential output: support both 10/100 Mbps speed,
meet 802.3/802.3u spec.
Twisted pair transmit differential output: support both 10/100 Mbps speed,
meet 802.3/802.3u spec.
NC pin : used in test mode only
RTX2EQ external resistor to ground: 1.4K ohm, 5%
RTX external resistor to ground: 560 ohm, 5%
PIN#
110
44
84
Pin Name
EECS
C46/C66
LED0(TXC)
Type
O,2ma
I,TTL
I/O,16ma
83 LED1(TXEN)
O,16ma
42,43 UPTYPE0,
I,TTL
42 UPTYPE0( MDIO) I/O,TTL
43 UPTYPE1(MDC) I/O, TTL
Description
EEPROM Chip Select Signal : Active high
EEPROM Size Select : Set for C46, reset for C66. Internal pull-up.
LED0 (TXC in MII mode) : When on-chip tranceiver is used, it is defined as
SPEED LED. When the light is on, it indicates the 100 Mbps speed. When
off, it indicates the 10 Mbps speed. When both LED0 and LED1 are flash-
ing identically, it means the bus integrity error. (Internal pull-up). When in
MII mode, this pin is defined as transmit clock TXC (25 MHz or 2.5 MHz)
input.
LED1 (TXEN in MII mode) :When on-chip tranceiver is used, it is defined
as Link/Activity LED. When the light is stable and on, it indicates a good
link. When flashing, it indicates TX and RX activities. When off, it means
a bad link. (Internal pull-up). When in MII mode, this pin is defined as trans-
mit enable TXEN pin.
uP type select control bit 1-0: UPTYPE1 and UPTYPE0 must be exter-
nally pull-up or down through < 4.7K ohm resistors to configure the bus
interface for different uP.
UPTYPE1
UPTYPE0
uP selected
0
0
reserved 0
0
1
80x1
1
0
80188
1
1
80186
uP type select control bit 0 ( MDIO in MII mode ): UPTYPE0 is
internally pull-down and used as uP type selection during host reset (
RSTB=0 ). After host reset sequence is completed, this pin become MDIO
pin if MII mode is selected.
uP type select control bit 1 ( MDC in MII mode ) : UPTYPE1 is internally
pull-down, after host reset sequence is completed , this pin become MDC
clock output pin if MII mode is selected.
P/N:PM0729
REV. 1.1, MAY. 28, 2001
7
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