MX98726EC Ver la hoja de datos (PDF) - Macronix International
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MX98726EC Datasheet PDF : 56 Pages
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MX98726EC
45
HOLD
O, 4ma Packet Memory Bus Hold Request : Active high to request Host to "float"
its interface of the packet memory. Host grants the packet buffer bus to
MX98726EC by asserting HLDA = 1.
46
HLDA
I, TTL
Packet Memory Bus Hold Acknowledge: Packet buffer bus is granted to
MX98726EC. If HLDA=0 then MX98726EC will float its interface on the
packet buffer. Internal pull-up.
77
PSENB
I, TTL
Host Program Strobe Enable : Active low to indicate current cycle is a
ROM access and MX98726EC will not decode this ROM cycle. PSENB
must high for packet memory access. Internal pull-up.
74
RSTB
I,TTL
Host Reset Input : Active low, Schmitt trigger input, Internal pull-up.
Packet Buffer Interface :
PIN# Pin Name
1,
MA[19:3]
115-119
7
MA19(RXD0)
Type
O,4ma
I/O, 4ma
6
MA18(RXD1) I/O, 4ma
5
MA17(RXD2) I/O, 4ma
4
MA16(RXD3) I/O, 4ma
90-96, MD[15:0]
98-104,
106-109
114
MA2(EEDO)
I/O,4ma
1/O,4ma
113
MA1(EEDI) 1/O,4ma
111
MA0(EECK) 1/O,4ma
87
86
88, 89
MOEB
MCSB
MWEB[1:0]
O,4ma
O,4ma
O,4ma
P/N:PM0729
Description
Memory Address Bit 19-0: If HLDA = 0 then all these address lines are tri-
stated.
Memory Address Bit19, when on-chip tranceiver is used, it is defined as
MA19, while in MII mode, it is used as receive data bit RXD0 pin.
Memory Address Bit18, when on-chip tranceiver is used, it is defined as
MA18, while in MII mode, it is used as receive data bit RXD1 pin.
Memory Address Bit17, when on-chip tranceiver is used, it is defined as
MA17, while in MII mode, it is used as receive data bit RXD2 pin.
Memory Address Bit16, when on-chip tranceiver is used, it is defined as
MA16, while in MII mode, it is used as receive data bit RXD3 pin.
Memory Data Bit 15-0 : Internal pull-down.
Memory Address Bit 2 or EEPROM Data Out bit: Right after host reset,
GMAC automatically load configuration information from external EEPROM.
During this period, MA2 pin acts as a EEDO pin that read in output data
stream from EEPROM. After EEPROM auto load sequence is done, this
pin becomes MA2 together with MA[19:3] forms packet buffer address
line 19 - 0. Internally pull-down.
Memory Address Bit 1 or EEPROM Data In bit: During EEPROM auto load
sequence, MA1 pin acts as EEDI pin that write data stream into EEPROM.
After EEPROM auto load sequence is done, this pin becomes MA1, to-
gether with MA[19:2] forms packet buffer address lines.
Memory Address Bit 0 or EEPROM Clock Input : During EEPROM auto
load sequence, MA0 pin acts as EECK pin that provides clock to EEPROM.
After EEPROM auto load sequence is done, this pin becomes MA0, to-
gether with MA[19:1] forms packet buffer address lines.
Memory Output Enable: Active low during packet buffer read access.
Memory Chip Select: Active low during packet buffer accesses.
Byte Write Enable: Active low during packet buffer write cycle. MWEB1 for
high byte and MWEB0 for low byte.
REV. 1.1, MAY. 28, 2001
6
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