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CDP1020

SMBus/I2C ACPI Dual Device Bay Controller

Intersil 

CDP1020

Bay Control and Enable Register, BCERx

The CDP1020 incorporates two separate bay control and

enable registers, one for each bay. The organization of these

two registers is identical. BCER0 is located at address $10;

BCER1 is at $18. Both BCER registers are cleared at reset.

BITS 31:8

Reserved. Always read as 0.

BIT 7, LOCK_CTL

The LOCK_CTL is a read/write bit that controls the software

controlled solenoid interlock for each bay. This bit has two

distinct modes of operation, depending on the value written

into the SOL[3:0] bits in the SFR.

If the SOL[3:0] bits in the SFR contain any nonzero value, the

LOCK_CTL bit logic is in “pulsed” mode. In pulse mode, the

SFTLOCK output will be asserted for a fixed time duration

when the LOCK_CTL is changed from a logic 1 to a logic 0.

Writing a 0 to this bit while it is already 0 has no effect. Writing

a 1 to this bit while it is a 0 will set the bit, but will not affect the

SFTLOCK output. The duration of the SFTLOCK pulse is

controlled by the SPD and SOL[3:0] bits in the SFR. Refer to

the Special Function Register text for more details.

If the SOL[3:0] bit in the SFR are all 0, the LOCK_CTL circuitry

is in “level” mode. In this case, the SFTLOCK output

corresponding to the LOCK_CTL bit will simply follow the state

of the LOCK_CTL bit. When the LOCK_CTL is set, the

SFTLOCK output will be high; likewise, when the LOCK_CTL

bit is clear, the SFTLOCK output will be low. Figure 7 shows the

relationship between the LOCK_CTL bit and its corresponding

SFTLOCK output in both level and pulsed modes.

BITS 6:4, BAY_STREQ[2:0]

This three bit field represents the state of the bay as requested

by the operating system. It does not necessarily represent the

actual state of the bay. The states are represented as such:

000

No change requested

001

Request Bay State = Device Inserted

010

Request Bay State = Device Enabled

011

Request Bay State = Removal Requested

100

Request Bay State = Removal Allowed

101

Reserved

110

Reserved

111

Reserved

If 000 is written, then no change to the current bay state is

requested and the current nonzero value of this field is

retained. This allows the operating system to modify other

bits in this register without affecting the bay state. A bay

state change will only occur when these fields are written if a

device is inserted (1394PRx & USBPRx = 0). These bits

may be read or written at any time by the operating system.

These bits are cleared by any hardware transition to the Bay

Empty State (i.e., device removal).

BIT 3, REMREQ_EN

This read/write bit allows the operating system to

enable/disable internal CDP1020 interrupts and bay state

transitions due to a logic “0” input value of the REMREQx

pin. If this bit is clear, the CDP1020 will not notify the OS and

will not transition the bay state to Removal Requested when

the REMREQx button has been pushed. If this bit is set after

the REMREQ_STS bit in the BSTR has been set, an

interrupt event will be generated and a bay status change

will occur. This bit is cleared by reset.

BIT 2, DEVSTSCHG_EN

This is a read/write bit that enables/disables internal

CDP1020 interrupt events and bay state transitions due to the

setting of the DEVSTSCHG bit in the BSTR. If this bit is clear,

the CDP1020 will not notify the OS whenever the bay state

has changed. The DEVSTSCHG bit in the BSTRx will still

reflect a bay state change.

The DEVSTSCHG_EN bit also allows the CDP1020 to

automatically transition the bay state to Device Inserted when

an insertion event is the cause of the DEVSTSCHG.

Hardware transitions to the Bay Empty state will always occur

on a device removal, regardless of the state of the

DEVSTSCHG_EN bit. This bit is cleared by reset.

BIT 1, REMEVTWAK_EN

This bit enables/disables internal CDP1020 interrupt events

due to device removal. This bit gates the device removal

event in the DEVSTSCHG logic (see Bay Status Register,

below). The intent is to conditionally allow device removal as

a wake-up event.

If clear, this bit will prevent the DEVSTSCHG flag in the BSTR

from being set when a device is removed and the bay is in the

Removal Allowed state. A hardware transition to the Bay

Empty state will still occur. This bit does not affect any of the

interrupt logic if the bay is not in the Removal Allowed state.

This bit is cleared by reset.

BIT 0, PWR_CTL

The PWR_CTL is the enable bit for the VID power rail. When

set, the internal logic of the CDP1020 will output the VGATE

voltage level on the PWREN pin associated with this register.

(Refer to the Power Enable System text for more details)

When clear, the PWREN pin will be pulled down to VSS by a

standard N-Channel output driver. This allows the gate voltage

of the VID control MOSFET to be discharged quickly and the

device switched off. No external pull down resistor is necessary.

This bit is cleared by reset. This bit cannot be set if there is

no device in the bay (1394PRx & USBPRx = 1) or if the

LOCK_CTL bit is clear. If set and a device is suddenly

removed (i.e., without OS permission), the CDP1020 will

clear this bit and disable the PWRENx output.

Note: A single write to the BCER may set both the LOCK_CTL

and PWR_CTL bits at the same time.

2-429

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