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CDP1020

SMBus/I2C ACPI Dual Device Bay Controller

Intersil 

CDP1020

Bay Status Register, BSTRx

Like the Bay Control and Enable register, there is one Bay

Status register associated with each bay controlled by the

CDP1020. The addresses for the BSTR registers are $14

(BSTR0) and $20 (BSTR1). Both BSTR registers are

cleared at reset.

BITS 31:11

Reserved, always read as 0.

BITS 10:8, BAY_FF[2:0]

This three bit field indicates the form factor of the controlled

bay:

000

001

010

011- 111

DB32

DB20

DB13

Reserved

These bits are write-once only bits after a power-on reset

and should be written by the system BIOS or the operating

system at start-up. Once written, these bits become read-

only. Subsequent internal and external resets do not affect

the write status of these bits. The value of these bits is

indeterminate at power on and are not affected by any type

of reset.

BIT 7, SL_STS

The read only SL_STS indicates the state of the external

security lock. This bit simply reflects the inverted state of the

SECUREx pin. If clear, external security lock is disengaged.

If set, the lock is engaged.

The state of this bit depends on the external state of the

SECUREx pin and the state of the SECLOCK bit in the

DBCCR register (see above). If the SECLOCK bit is clear,

this bit will always read as a “0”. If SECLOCK is set, the state

of this bit will reflect the inverted state of the SECUREx pin.

BIT 6:4, BAY_ST[2:0]

This three bit field represents the actual state of the bay. These

bits are read only. The bay state is represented as such:

000

Bay Empty

001

Device Inserted

010

Device Enabled

011

Removal Requested

100

Device Removal Allowed

101

Reserved

110

Reserved

111

Reserved

Bay states and how they are controlled is described in the

State Machine Logic text.

BIT 3, REMREQ_STS

This bit indicates that the removal request button for this

bay has been pressed (REMREQx pin has been driven

low). This bit is referred to as a “sticky status bit”; once set,

the you must write a “1” to this bit position to clear it. If the

REMREQ_EN bit in the associated control register is set,

the CDP1020 will generate a REMREQ interrupt event

when this bit is set. A REMREQ interrupt event will cause a

hardware transition of the bay state to Removal Allowed

and assert the ALRT pin of the CDP1020 to notify the OS

of the REMREQx button press.

BIT 2, DEVSTSCHG

This bit indicates that a hardware event has occurred that

has changed the status of the device bay. This could be

caused by a device insertion or a device removal. This bit,

like the REMREQ_STS bit, is a sticky status bit; once set,

the OS must write a “1” to clear it.

This bit will be set on all device removals except when the

REMEVTWAK_EN bit in the BCER is clear and the bay is in the

Removal Allowed state.

If the DEVSTSCHG bit is set due to an insertion event and

the DEVSTSCHG_EN bit in the BCER is set, the CDP1020

will hardware transition the bay state to Device Inserted and

assert the ALRT pin to notify the system of the insertion.

This bit is cleared by reset.

BIT 1, 1394PRSN_STS

This bit reflects the inverted state of the 1394PRx pin

associated with this status register. If the 1394PRx pin is

high, this bit will read cleared. If the 1394PRx pin is low

(1394 device inserted) this pin will read high. The setting of

this bit can generate a device status change event. This bit is

cleared by reset.

BIT 0, USBPRSN_STS

This bit reflects the inverted state of the USBPRx pin

associated with this status register. If the USBPRx pin is

high, this bit will read cleared. If the USBPRx pin is low (USB

device inserted) this pin will read high. The setting of this bit

can generate a device status change event. This bit is

cleared by reset.

2-430

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