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AD1852 Datasheet PDF : 20 Pages
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AD1852
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND 1
MCLK 2
CLATCH 3
CCLK 4
CDATA 5
NC 6
192/48 7
ZEROR 8
DEEMP 9
96/48 10
AGND 11
OUTR+ 12
OUTR– 13
FILTER 14
AD1852
TOP VIEW
(Not to Scale)
28 DVDD
27 SDATA
26 BCLK
25 LRCLK
24 RESET
23 MUTE
22 ZEROL
21 IDPM0
20 IDPM1
19 FILTB
18 AVDD
17 OUTL+
16 OUTL–
15 AGND
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. Mnemonic Input/Output
1
DGND
I
2
MCLK
I
3
CLATCH
I
4
CCLK
I
5
CDATA
I
6
NC
7
192/48
I
8
ZEROR
O
9
DEEMP
I
10
96/48
I
11, 15 AGND
I
12
OUTR+
O
13
OUTR−
O
14
FILTR
O
16
OUTL−
O
17
OUTL+
O
18
AVDD
I
19
FILTB
20
IDPM1
I
21
IDPM0
I
22
ZEROL
O
23
MUTE
I
24
RESET
I
Description
Digital Ground.
Master Clock Input. Connect to an external clock source running at either 256 fS, 384 fS, 512 fS,
768 fS, or 1024 fS.
Latch Input for SPI Control Data Port. This input is rising-edge sensitive.
SPI Control Clock Input for Control Data. Control input data must be valid on the rising edge of
CCLK. CCLK may be continuous or gated.
SPI Control Data Input, MSB First. SPI data port for controlling AD1852 functions as described in
the SPI Register Definitions section.
No Connect.
192 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 192 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 11 of the control register.
Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input
for more than 1024 LR clock cycles.
De-Emphasis. Digital de-emphasis is enabled when this input signal is high. This is used to
impose a 50 μs/15 μs response characteristic on the output audio spectrum at an assumed
44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via the SPI
control register.
96 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 96 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 10 of the control register.
Analog Ground.
Right Channel Positive Line Level Analog Output.
Right Channel Negative Line Level Analog Output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference
with parallel 10 μF and 0.1 μF capacitors to the AGND.
Left Channel Negative Line Level Analog Output.
Left Channel Positive Line Level Analog Output.
Analog Power Supply. Connect this pin to the analog 5 V supply.
Filter Capacitor Connection. Connect 10 μF||10 nF capacitor to AGND (Pin 15).
Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input
for more than 1024 LR clock cycles.
Mute. Assert this pin high to mute both stereo analog outputs. De-assert low for normal operation.
Reset. The AD1852 is reset on the rising edge of this signal. The serial control port registers are
reset to the default values. For normal operation, assert this pin high.
Rev. A | Page 7 of 20
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