AD1852 Ver la hoja de datos (PDF) - Analog Devices
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AD1852 Datasheet PDF : 20 Pages
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AD1852
Pin No.
25
26
27
28
Mnemonic
LRCLK
BCLK
SDATA
DVDD
Input/Output
I
I
I
I
Description
Left/Right Clock Input for Serial Audio Data Input Port. This pin must run continuously.
Bit Clock Input for Serial Audio Data Input Port. This pin need not run continuously; may be
gated or used in a burst fashion.
Serial Audio Data Input, MSB First. Input for the serial audio data stream is as described the
in Serial Data Input Port section.
Digital Power Supply. Connect this pin to the digital 5 V supply.
Table 12. Serial Data Input Mode
IDPM1 (Pin 20)
0
0
1
1
IDPM0 (Pin 21)
0
1
0
1
Serial Data Input Format
Right justified
I2S compatible
Left justified
DSP
LRCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
LSB
INPUT
LRCLK
INPUT
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
Figure 3. Right-Justified Mode
LEFT CHANNEL
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB
Figure 4. I2S-Justified Mode
LRCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
LRCLK
INPUT
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
LEFT CHANNEL
MSB MSB–1 MSB–2
Figure 5. Left-Justified Mode
LSB+2 LSB+1 LSB
RIGHT CHANNEL
MSB MSB–1
BCLK
INPUT
SDATA
INPUT
LRCLK
INPUT
MSB MSB–1
LSB+2 LSB+1 LSB
LEFT CHANNEL
MSB MSB–1
Figure 6. Left-Justified DSP Mode
RIGHT CHANNEL
LSB+2 LSB+1 LSB
MSB MSB–1
BCLK
INPUT
SDATA
INPUT
LSB
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
MSB MSB–1 MSB–2
Figure 7. 32 × fS Packed Mode
LSB+2 LSB+1 LSB
MSB MSB–1
Rev. A | Page 8 of 20
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