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IDT72264L15PF
Integrated Device Technology
IDT72264L15PF Datasheet PDF : 31 Pages
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IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
Finally,of all SuperSync FIFOs, the IDT72264/72274 offer
the lowest dynamic power dissipation.
These devices meet a wide variety of data buffering needs.
In addition to those already mentioned, applications include
such as optical disk controllers, Local Area Networks (LANs),
and inter-processor communication.
Both FIFOs have an 18-bit input port (Dn) and an 18-bit
output port (Qn). The input port is controlled by a free-running
clock (WCLK) and a data input enable pin (WEN). Data is
written into the synchronous FIFO on every clock when WEN
is asserted. The output port is controlled by another clock pin
(RCLK) and enable pin (REN). The read clock can be tied to
the write clock for single clock operation or the two clocks can
run asynchronously for dual clock operation. An output
enable pin (OE) is provided on the read port for three-state
control of the outputs.
The IDT72264/72274 have two modes of operation: In the
IDT Standard Mode, the first word written to the FIFO is
deposited into the memory array. A read operation is required
to access that word. In the First Word Fall Through Mode
(FWFT), the first word written to an empty FIFO appears
automatically on the outputs, no read operation required. The
state of the FWFT/SI pin during Master Reset determines the
mode in use.
The IDT72264/72274 have five flag functions, EF/OR
(Empty Flag or Output Ready), FF/IR (Full Flag or Input
Ready), and HF (Half-full Flag). The EF and FF functions are
selected in the IDT Standard Mode.
The IR and OR functions are selected in the First Word Fall
Through Mode. IR indicates that the FIFO has free space to
receive data. OR indicates that data contained in the FIFO is
available for reading.
HF is a flag whose threshold is fixed at the half-way point in
memory. This flag can always be used irrespective of mode.
PAE and PAF can be programmed independantly to any
point in memory. They, also, can be used irrespective of
mode. Programmable offsets determine the flag threshold
and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, such that PAE can be
set at 127 or 1023 locations from the empty boundary and the
PAF threshold can be set at 127 or 1023 locations from the full
boundary. All these choices are made with LD during Master
Reset.
PIN CONFIGURATIONS
PIN 1
WEN
SEN
FS
VCC
MAC
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Q17
Q16
GND
Q15
Q14
VCC
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
3218 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
NOTES:
1. When the data path is selected to be 9 bits wide (MAC is HIGH), D9 - D17 may either be tied to ground or left open, Q9 - Q17 must be left open.
2
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