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IDT72264L15PF

VARIABLE WIDTH SUPERSYNC™ FIFO 8,192 x 18 or 16,384 x 9 16,384 x 18 or 32,768 x 9

Integrated Device Technology 

IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™

(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)

COMMERCIAL TEMPERATURE RANGES

Symbol

fS

tA

tCLK

tCLKH

tCLKL

tDS

tDH

tENS

tENH

tLDS

tLDH

tRS

tRSS

tRSR

tRSF

tFWFT

tRTS

tOLZ

tOE

tOHZ

tWFF

tREF

tPAF

tPAE

tHF

tSKEW1

tSKEW2

Parameter

Clock Cycle Frequency

Data Access Time

Clock Cycle Time

Clock High Time

Clock Low Time

Data Set-up Time

Data Hold Time

Enable Set-up Time

Enable Hold Time

Load Set-up Time

Load Hold Time

Reset Pulse Width(3)

Reset Set-up Time

Reset Recovery Time

Reset to Flag and Output Time

Mode Select Time

Retransmit Set-Up Time

Output Enable to Output in Low Z(4)

Output Enable to Output Valid

Output Enable to Output in High Z(4)

Write Clock to FF or IR

Read Clock to EF or OR

Write Clock to PAF

Read Clock to PAE

Clock to HF

Skew time between RCLK and WCLK

for FF and IR

Skew time between RCLK and

WCLK for PAE and PAF

Commercial

72264L15

72274L15

Min.

Max.

—

66.7

2

10

15

—

6

—

6(2)

—

4

—

1

—

4

—

1

—

4

—

10

—

15

—

15

—

15

—

—

15

0

—

4

—

0

—

3

8

3

8

—

10

—

10

—

10

—

10

—

20

12

—

21

—

Commercial

72264L20

72274L20

Min.

Max.

—

50

2

12

20

—

8

—

8

—

5

—

1

—

5

—

1

—

5

—

10

—

20

—

20

—

20

—

—

20

0

—

5

—

0

—

3

10

3

10

—

12

—

12

—

12

—

12

—

22

15

—

25

—

Unit

MHz

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

NOTES:

1. All AC timings apply to both Standard IDT Mode and First Word Fall

Through Mode.

2. For the RCLK line: tCLKL (min.) = 7 ns only when reading the offsets from

the programmable flag registers; otherwise, use the table value. For the

WCLK line, use the tCLKL (min.) value given in the table.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns

1.5V

1.5V

See Figure 1

3037 tbl 08

5V

D.U.T.

680Ω

1.1K

30pF*

3218 drw 04

Figure 1. Output Load

* Includes jig and scope capacitances.

6

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