IDT72264L15PF Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT72264L15PF
Integrated Device Technology
IDT72264L15PF Datasheet PDF : 31 Pages
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IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
When the REN input is HIGH, the output register holds the
previous data and no new data is loaded into the output
register.
In the IDT Standard Mode, every word accessed at Qn,
including the first word written to an empty FIFO, must be
requested using REN. When all the data has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further
read operations. REN is ignored when the FIFO is empty.
Once a write is performed, EF will go HIGH after tFWL1 +tREF
and a read is permitted.
In the FWFT Mode, the first word written to an empty FIFO
automatically goes to the outputs Qn, no need for any read
request. In order to access all other words, a read must be
executed using REN . When all the data has been read from
the FIFO, Output Ready (OR) will go HIGH, inhibiting further
read operations. REN is ignored when the FIFO is empty.
Once a write is performed, OR will go LOW after tFWL2 +tREF,
when the first word appears at Qn ; if a second word is written
into the FIFO, then REN can be used to read it out.
SERIAL ENABLE (SEN)
The SEN input is an enable used only for serial program-
ming of the offset registers. The serial programming method
must be selected during Master Reset. SEN is always used
in conjunction with LD. When these lines are both LOW, data
at the SI input can be loaded into the input register one bit for
each LOW-to-HIGH transition of WCLK.
When SEN is HIGH, the programmable registers retains
the previous settings and no offsets are loaded.
SEN functions the same way in both IDT Standard and
FWFT modes.
LD WEN REN SEN WCLK
0
0
11
0
1
0
1
X
0
1
1
0
X
1
11
X
RCLK
X
X
X
MAC = Vcc
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Selection
MAC = GND
Parallel write to registers:
Empty Offset
Full Offset
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset
Full Offset
Serial shift into registers:
28 bits for the 72264
30 bits for the 72274
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial shift into registers:
26 bits for the 72264
28 bits for the 72274
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
No Operation
No Operation
1
0XX
X
Write Memory
Write Memory
1
X
0X
X
Read Memory
Read Memory
1
1
1X
X
X
No Operation
No Operation
NOTES:
1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.
2. The programming method can only be selected at Master Reset.
3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
4. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 2. Partial Flag Programming Sequence
3218 tbl 01
9
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