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CIRCC

Consumer Infrared Communications Controller

SMSC -> Microchip 

CHIP-LEVEL CIrCC ADDRESSING SUPPORT

CIrCC Register addressing is controlled at the

chip level. Both the ACE bank select, nACE, and

the SCE bank select, nSCE, are decoded at the

chip level from the host address bus to

access data in the CIrCC register banks (Figure

38). Figure 38 illustrates a chip-level CIrCC

address decoder using a base address of

‘400’hex.

Address Bus

AEN

I/O Select

ACE

Chip-Level Select

Address

Decoder

SCE

Select

nACE

IrCC

nSCE

FIGURE 38 - CHIP-LEVEL CIRCC ADDRESS DECODE

Table 32 - CIrCC Address Decode at '400'hex

HEX ADDRESS

nACE nSCE

DESCRIPTION

000 - 3FF

1

1 CIrCC registers not accessible

400 - 407

0

1 ACE UART registers enabled

408 - 40F

1

0 SCE registers enabled

410 - 4FF

1

1 CIrCC registers not accessible

68

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