DM9008 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9008 Datasheet PDF : 68 Pages
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Register Descriptions
DM9008
ISA/Plug & Play Super Ethernet Contoller
Configuration Register A (CRA)
Configuration Register A can be read at address 0AH in Page 0 of ENC, and can be written by following a read to address 0AH with a
write to address 0AH. If address 0AH is written without a previous read to 0AH, the write will be regarded as a write to register RBCR0
of ENC.
7
6
5
4
3
2
1
0
FREAD INT2 INT1 INT0 IOAD3 IOAD2 IOAD1 IOAD0
Bit
0-3
4-6
7
Symbol
IOAD0
IOAD1
IOAD2
IOAD3
INT0
INT1
INT2
FREAD
Description
I/O Address: These three bits determine the base I/O address of DM9008 within the PC
system's I/O map
bit3
bit2
bit1
bit0
I/O base
0
0
0
0
300H
0
0
0
1
320H
0
0
1
0
340H
0
0
1
1
360H
0
1
0
0
380H
0
1
0
1
3A0H
0
1
1
0
3C0H
0
1
1
1
3E0H
bit3
bit2
bit1
bit0
I/O base
1
0
0
0
200H
1
0
0
1
220H
1
0
1
0
240H
1
0
1
1
260H
1
1
0
0
280H
1
1
0
1
2A0H
1
1
1
0
2C0H
1
1
1
1
2E0H
Interrupt Pin Mapping: Only one interrupt output pin will be driven active when a valid
interrupt condition occurs
bit5
bit4
bit3
Interrupt
0
0
0
IRQ3
0
0
1
IRQ4
0
1
0
IRQ5
0
1
1
IRQ9
1
0
0
IRQ10
1
0
1
IRQ11
1
1
0
IRQ12
1
1
1
IRQ15
Fast Read: In the remote DMA read mode. When this bit is set high, the DM9008 will begin
the next port fetch before the current IOR is completed
10
Final
Version: DM9008-DS-F02
November 30, 2000
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