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DM9008

ISA/Plug & Play Super Ethernet Contoller

Davicom Semiconductor, Inc. 

MAR0

D7

FB7

D6

FB6

D5

FB5

D4

FB4

D3

FB3

D2

FB2

D1

FB1

D0

FB0

MAR1 FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8

MAR2 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16

MAR3 FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24

MAR4 FB39 FB38 FB37 FB36 FB35 FB34 FB33 FB32

MAR5 FB47 FB46 FB45 FB44 FB43 FB42 FB41 FB40

MAR6 FB55 FB54 FB53 FB52 FB51 FB50 FB49 FB48

MAR7 FB63 FB62 FB61 FB60 FB59 FB58 FB57 FB56

DMA Registers

Local DMA Transmit Registers

15

8

7

0

(TPSR) PAGE START

(TBCR0,1) TRANSMIT BYTE COUNT

Local DMA Receive Registers

15

8

7

0

(PSTART) PAGE START

(PSTOP) PAGE STOP

(CURR) CURRENT

(BRNY) BOUNDARY

(CLDA0,1) CURRENT LOCAL DMA ADDRESS

Remote DMA Registers

15

8

7

0

(RSAR0,1) START ADDRESS

(RBCR0,1) BYTE COUNT

(CRAD0,1) CURRENT REMOTE DMA ADDRESS

DM9008

ISA/Plug & Play Super Ethernet Contoller

(i) Local DMA Transmit Registers

Transmit Page Start Register (TPSR)

This register points to the assembled packet to be transmitted.

Since all transmit packets are assembled on 256-byte page

boundaries, only the eight higher order addresses are

specified.

7

6

5

4

3

2

1

0

A15 A14 A13 A12 A11 A10 A9 A8

Transmit Byte Counter Register 0,1 (TBCR0,TBCR1)

These two registers indicate the length of the packet to be

transmitted in bytes. The maximum number of transmit bytes

allowed is 64K bytes. The DM9008 will not truncate

transmissions longer than 1500 bytes.

7

6

5

4

32

10

TBCR1 L15 L14 L13 L12 L11 L10 L9 L8

7

6

5

43

2

10

TBCR0 L7 L6 L5 L4 L3 L2 L1 L0

(ii) Local DMA Receive Registers

Page Start, Stop Registers (PSTART, PSTOP)

The Page Start and Page Stop Registers program the starting

and stopping page of the Receive Buffer RAM. Since the

DM9008 uses fixed 256-byte buffers aligned on page

boundaries, only the upper eight bits of the start and stop

address are specified.

7

6

5

43

2

10

PSTART

PSTOP

A15

A14

A13

A12

A11

A10

A9

A8

Boundary Register (BNRY)

This register is used to prevent overflow of the Receive Buffer

Ring. Buffer management compares the contents of this

register to the next buffer address when linking buffers

together. If the contents of this register match the next buffer

address, the local DMA operation is aborted.

7

6

54

3

2

10

BNRY A15 A14 A13 A12 A11 A10 A9 A8

24

Final

Version: DM9008-DS-F02

November 30, 2000

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