LPC47B37X Ver la hoja de datos (PDF) - SMSC -> Microchip

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LPC47B37X

100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications

SMSC -> Microchip 

The other GPIOs function as follows:

GP40, GP62:

• Buffers powered by VCC, but in the absence

of VCC they are backdrive protected. These

pins do not have input buffers into the

wakeup logic that are powered by VTR.

These pins are not used for wakeup.

GP42, GP53, GP60, GP61:

• Buffers powered by VTR.

GP42 is the nIO_PME pin.

GP53 has IRTX as the alternate function and its

output buffer is powered by VTR so that the pin

is always forced low on VTR POR, VCC POR

and Hard Reset. The IRTX pin

(GP53/TXD2/IRTX) is powered by VTR so that it

is driven low when VCC = 0V with VTR =3.3V.

This pin is driven low on VTR POR, VCC POR

and Hard Reset regardless of the selected pin

function and regardless of the state of internal

PWRGOOD (i.e., when VCC=3.3V and when

VCC=0V with VTR=3.3V). The GP53/TXD2/IRTX

pin will remain low following a VCC POR until the

IRTX function is selected and the serial port is

enabled by setting the activate bit, at which time

the pin will reflect the state of the IR transmit

output of the IR block. If the TXD2 function is

selected for the pin, it will remain low following a

VCC POR until the serial port is enabled by

setting the activate bit, at which time the pin will

reflect the state of the transmit output of the

serial port. If the GPIO output function is

selected, the pin will reflect the state of the data

bit.

GP60 and GP61 are used for the LED functions.

See the Table in the GPIO section for more

information.

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