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LPC47B37X

100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications

SMSC -> Microchip 

I/O and DMA START Fields

I/O and DMA cycles use a START field of 0000.

Reset Policy

The following rules govern the reset policy:

1) When nPCI_RESET goes inactive (high),

the clock is assumed to have been running

for 100usec prior to the removal of the reset

signal, so that everything is stable. This is

the same reset active time after clock is

stable that is used for the PCI bus.

2) When nPCI_RESET goes active (low):

a) The host drives the nLFRAME signal

high, tristates the LAD[3:0] signals, and

ignores the nLDRQ signal.

b) The LPC47B37x ignores nLFRAME,

tristate the LAD[3:0] pins and drive the

nLDRQ signal inactive (high).

LPC Transfers

Wait State Requirements

I/O Transfers

The LPC47B37x inserts three wait states for an

I/O read and two wait states for an I/O write

cycle. A SYNC of 0110 is used for all I/O

transfers. The exception to this is for transfers

where IOCHRDY would normally be deasserted

in an ISA transfer (i.e., EPP) in which case the

sync pattern of 0110 is used and a large number

of syncs may be inserted (up to 330 which

corresponds to a timeout of 10us).

DMA Transfers

The LPC47B37x inserts three wait states for a

DMA read and four wait states for a DMA write

cycle. A SYNC of 0101 is used for all DMA

transfers.

See the example timing for the LPC cycles in the

“Timing Diagrams” section.

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