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LPC47B37X

100 Pin Enhanced Super I/O for LPC Bus with SMBus Controller for Commercial Applications

SMSC -> Microchip 

LPC Interface

The following sub-sections specify the implementation of the LPC bus.

LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use

PCI 33MHz electrical signal characteristics.

SIGNAL NAME TYPE

LAD[3:0]

I/O

nLFRAME

Input

nPCI_RESET

nLDRQ

nIO_PME

nLPCPD

Input

Output

OD

Input

SER_IRQ

PCI_CLK

I/O

Input

DESCRIPTION

LPC address/data bus. Multiplexed command, address and data

bus.

Frame signal. Indicates start of new cycle and termination of broken

cycle

PCI Reset. Used as LPC Interface Reset.

Encoded DMA/Bus Master request for the LPC interface.

Power Mgt Event signal. Allows the LPC47B37x to request wakeup.

Powerdown Signal. Indicates that the LPC47B37x should prepare

for power to be shut on the LPC interface.

Serial IRQ.

PCI Clock.

LPC Cycles

The following cycle types are supported by the LPC protocol.

CYCLE TYPE

TRANSFER SIZE

I/O Write

1 Byte Transfer

I/O Read

1 Byte Transfer

DMA Write

1 Byte

DMA Read

1 Byte

The LPC47B37x ignores cycles that it does not support.

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