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LPC47N227-MN

100 Pin Super I/O with LPC Interface for Notebook Applications

SMSC -> Microchip 

FLOPPY DISK CONTROLLER

The Floppy Disk Controller (FDC) provides the

interface between a host microprocessor and the

floppy disk drives. The FDC integrates the

functions of the Formatter/Controller, Digital Data

Separator, Write Precompensation and Data Rate

Selection logic for an IBM XT/AT compatible FDC.

The true CMOS 765B core guarantees 100% IBM

PC XT/AT compatibility in addition to providing

data overflow and underflow protection.

The FDC is compatible to the 82077AA using

SMSC's proprietary floppy disk controller core.

The LPC47N227 supports one floppy disk drive

directly through the FDC interface pins and two

floppy disk drives via the FDC interface on the

parallel port pins. It can also be configured to

support one drive on the FDC interface pins and

one drive on the parallel port pins.

FDC Internal Registers

The Floppy Disk Controller contains eight internal

registers that facilitate the interfacing between the

host microprocessor and the disk drive. Table 2

shows the addresses required to access these

registers. Registers other than the ones shown are

not supported. The rest of the description

assumes that the primary addresses have been

selected.

PRIMARY

ADDRESS

3F0

3F1

3F2

3F3

3F4

3F4

3F5

3F6

3F7

3F7

Table 2 – Status, Data and Control Registers

(Shown with base addresses of 3F0 and 370)

SECONDARY

ADDRESS

R/W

REGISTER

370

R

Status Register A (SRA)

371

R

Status Register B (SRB)

372

R/W Digital Output Register (DOR)

373

R/W Tape Drive Register (TDR)

374

R

Main Status Register (MSR)

374

W Data Rate Select Register (DSR)

375

R/W Data (FIFO)

376

Reserved

377

R

Digital Input Register (DIR)

377

W Configuration Control Register (CCR)

Status Register A (SRA)

Address 3F0 READ ONLY

This register is read-only and monitors the state

of the internal interrupt signal and several disk

interface pins in PS/2 and Model 30 modes. The

SRA can be accessed at any time when in PS/2

mode. In the PC/AT mode the data bus pins D0

- D7 are held in a high impedance state for a

read of address 3F0.

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