LPC47N227-MN Ver la hoja de datos (PDF) - SMSC -> Microchip
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LPC47N227-MN Datasheet PDF : 202 Pages
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BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller
clock and data separator circuits will be turned off. The controller will come out of manual low power mode
after a software reset or access to the Data Register or Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self
clearing.
Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, located in the
Configuration section (CR14).
Table 7 – Precompensation Delays
PRECOMP
PRECOMPENSATION
432
DELAY (nsec)
<2Mbps
2Mbps
111
0.00
0
001
41.67
20.8
010
83.34
41.7
011
125.00
62.5
100
166.67
83.3
101
208.33
104.2
110
250.00
125
000
Default
Default
Default: See Table 10
DRIVE RATE
Table 8 – Data Rates
DATA RATE
DATA RATE
DRT1 DRT0 SEL1 SEL0 MFM FM
0
0
1
1
1Meg
---
0
0
0
0
500
250
0
0
0
1
300
150
0
0
1
0
250
125
0
1
1
1
1Meg
---
0
1
0
0
500
250
0
1
0
1
500
250
0
1
1
0
250
125
1
0
1
1
1Meg
---
1
0
0
0
500
250
1
0
0
1
2Meg
---
1
0
1
0
250
125
DENSEL
1
1
0
0
1
1
0
0
1
1
0
0
DRATE(1)
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
Drive Rate Table (Recommended)
00 = 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format
01 = 3-Mode Drive
10 = 2 Meg Tape
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