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COM20022I

10Mbps ARCNET controller with 2Kx8 on-board RAM

SMSC -> Microchip 

Note 2:Tolerance on the position of the leads is ± 0.04 mm maximum.

Note 3:Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold

protrusion is 0.25 mm.

Note 4: Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is

0.78-1.08 mm.

Note 5:Details of pin 1 identifier are optional but must be located within the zone indicated.

APPENDIX A

This appendix describes the function of the NOSYNC and EF bits.

NOSYNC Bit

The NOSYNC bit controls whether or not the RAM initialization sequence requires the line to be idle by

enabling or disabling the SYNC command during initialization. It is defined as follows:

NOSYNC: Enable/Disable SYNC command during initialization. NOSYNC=0, Enable (Default): the line

has to be idle for the RAM initialization sequence to be written, NOSYNC=1, Disable: the line does not

have to be idle for the RAM initialization sequence to be written.

The following discussion describes the function of this bit:

During initialization, after the CPU writes the Node ID, the COM20022 will write "D1"h data to Address

000h and Node-ID to Address 001h of its internal RAM within 3uS. These values are read as part of the

diagnostic test. If the D1 and Node-ID initialization sequence cannot be read, the initialization routine

will report it as a device diagnostic failure. These writes are controlled by a micro-program which

sometimes waits if the line is active; SYNC is the micro-program command that causes the wait. When

the micro-program waits, the initial RAM write does not occur, which causes the diagnostic error. Thus

in this case, if the line is not idle, the initialization sequence may not be written, which will be reported

as a device diagnostic failure.

However, the initialization sequence and diagnostics of the COM20022 should be independent of the

network status. This is accomplished through some additional logic to decode the program counter,

enabled by the NOSYNC bit. When it finds that the micro-program is in the initialization routine, it

disables

the SYNC command. In this case, the initialization will not be held up by the line status.

Thus, by setting the NOSYNC bit, the line does not have to be idle for the RAM initialization sequence

to be written.

EF Bit

The EF bit controls several modifications to internal operation timing and logic. It is defined as follows:

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