COM20022I Ver la hoja de datos (PDF) - SMSC -> Microchip

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COM20022I

10Mbps ARCNET controller with 2Kx8 on-board RAM

SMSC -> Microchip 

Otherwise, every time the soft reset happens, the COM20020 Rev. B generates an unnecessary

interrupt since the status bits RI and TA are back to one by the soft reset.

This is resolved by changing the logic to reset the Mask register both by the hard reset and by the soft

reset. The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to

High in the Configuration register. This solution is Enabled/Disabled by the EF bit.

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