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LPC47B27X

100 Pin Enhanced Super I/O Controller with LPC Interface

SMSC -> Microchip 

BLOCK DIAGRAM

SER_IRQ

PCI_CLK

LPC Bus

Signals

SERIAL

IRQ

LPC BUS

INTERFACE

VTR Vcc Vss

nIO_SMI nIO_PME

SMI PME WDT

Game Port Signals*

... (1-Dual)

Game Port

FAN1* FAN_TACH1*

FAN2*

FAN_TACH2*

Fan

Control

DATA BUS

MULTI-MODE

PARALLEL

PORT/FDC

MUX

PD0-7

BUSY, SLCT, PE,

nERROR, nACK

nSTB, nSLCTIN,

nINIT , nALF

ADDRESS BUS

GENERAL

PURPOSE

I/O

GP1[0:7]*

GP2[0:2,4:7]*

GP3[0:7]*, GP4[0:3]*

GP5[0:7]*, GP6[0:1]*

ACPI

BLOCK

CONFIGURATION

REGISTERS

CONTROL BUS

16C550

COMPATIBLE

SERIAL

PORT 1

TXD1, nCTS1, nRTS1

RXD1

nDSR1, nDCD1, nRI1, nDTR1

WDATA

WCLOCK

SMSC

PROPRIETARY

DIGITAL

82077

COMPATIBLE

VERTICAL

FLOPPYDISK

CONTROLLER

DATA

SEPARATOR

WITH WRITE

PRECOM-

PENSATION

CORE

RCLOCK

16C550

COMPATIBLE

SERIAL

PORT 2 WITH

INFRARED

IRRX, IRTX

TXD2(IRTX), nCTS2, nRTS2*

RXD2(IRRX)*

nDSR2, nDCD2, nRI2, nDTR2*

MPU-401

SERIAL

PORT

MIDI_IN

MIDI_OUT

CLOCK

GEN

RDATA

8042

KCLK

KDATA

MCLK

MDATA

GATEA20, KRESET

nINDEX DENSEL nDS0

nTRK0 nDIR nMTR0

nDSKCHG

nSTEP

nWDATA

DRVDEN0

nRDATA

CLK32 CLOCKI nWRPRT nHDSEL DRVDEN1*

32KHz 14MHz nWGATE

* Denotes Multifunction Pins

FIGURE 1 – LPC47B27x BLOCK DIAGRAM

REFERENCE DOCUMENTS

1. SMSC Consumer Infrared Communications Controller (CIrCC) V1.X

2. IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993.

3. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook.

4. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997.

5. Low Pin Count (LPC) Interface Specification, Revision 1.0, September 29, 1997, Intel Document.

6. SMSC Application Note, AN 8-8: Using the Enhanced Keyboard and Mouse Wakeup Feature in SMSC Super I/O

Parts.

7. SMSC Application Note, AN 9-3: Application Considerations When Using the Powerdown Feature of SMSC

Floppy Disk Controllers.

3 VOLT OPERATION / 5 VOLT TOLERANCE

The LPC47B27x is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that

is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.

The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are:

• LAD[3:0]

• nLFRAME

• nLDRQ

• nLPCPD

The input voltage for all other pins is 5.5V max. These pins include all non-LPC Bus pins and the following pins:

• nPCI_RESET

• PCI_CLK

• SER_IRQ

• nIO_PME

SMSC LPC47B27x

- 13 -

DATASHEET

Rev. 04-17-07

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