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LPC47B27X

100 Pin Enhanced Super I/O Controller with LPC Interface

SMSC -> Microchip 

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately

after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and

configuration register block can be moved via the configuration registers. Some addresses are used to access more

than one register.

HOST PROCESSOR INTERFACE (LPC)

The host processor communicates with the LPC47B27x through a series of read/write registers via the LPC interface.

The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or

DMA transfers. All registers are 8 bits wide.

Table 1 - Super I/O Block Addresses

LOGICAL

ADDRESS

BLOCK NAME

DEVICE

Base+(0-5) and +(7)

Floppy Disk

0

Base+(0-7)

Serial Port Com 1

4

Base1+(0-7)

Serial Port Com 2

5

Base2+(0-7)

Parallel Port

3

Base+(0-3)

SPP

Base+(0-7)

EPP

Base+(0-3), +(400-402)

ECP

Base+(0-7), +(400-402)

ECP+EPP+SPP

60, 64

KYBD

7

Base + 0

Game Port

9

Base + (0-5F)

Runtime Registers

A

Base + (0-1)

MPU-401

B

Base + (0-1)

Configuration

NOTES

IR Support

Consumer IR

Note 1: Refer to the configuration register descriptions for setting the base address.

LPC INTERFACE

The following sub-sections specify the implementation of the LPC bus.

LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz

electrical signal characteristics.

SIGNAL NAME

LAD[3:0]

nLFRAME

nPCI_RESET

nLDRQ

nIO_PME

nLPCPD

SER_IRQ

PCI_CLK

TYPE

I/O

Input

Input

Output

OD

Input

I/O

Input

DESCRIPTION

LPC address/data bus. Multiplexed command, address and data bus.

Frame signal. Indicates start of new cycle and termination of broken

cycle

PCI Reset. Used as LPC Interface Reset.

Encoded DMA/Bus Master request for the LPC interface.

Power Mgt Event signal. Allows the LPC47B27x to request wakeup.

Powerdown Signal. Indicates that the LPC47B27x should prepare for

power to be shut on the LPC interface.

Serial IRQ.

PCI Clock.

Note: The nCLKRUN signal is not implemented in this part.

SMSC LPC47B27x

- 18 -

DATASHEET

Rev. 04-17-07

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