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LPC47B27X

100 Pin Enhanced Super I/O Controller with LPC Interface

SMSC -> Microchip 

POWER MANAGEMENT

CLOCKRUN Protocol

The CLKRUN# pin is not implemented in the LPC47B27x.

See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1.

LPCPD Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2.

SYNC Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2.1.8 for a table of valid SYNC values.

Typical Usage

The SYNC pattern is used to add wait states. For read cycles, the LPC47B27x immediately drives the SYNC pattern

upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the LPC47B27x needs to

assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or

1001. The LPC47B27x will choose to assert 0101 or 0110, but not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.

The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few

clocks. The LPC47B27x uses a SYNC of 0101 for all wait states in a DMA transfer.

The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP

cycles, where the number of wait states could be quite large (>1 microsecond). However, the LPC47B27x uses a

SYNC of 0110 for all wait states in an I/O transfer.

The SYNC value is driven within 3 clocks.

SYNC Timeout

The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it

will abort the cycle.

The LPC47B27x does not assume any particular timeout. When the host is driving SYNC, it may have to insert a

very large number of wait states, depending on PCI latencies and retries.

SYNC Patterns and Maximum Number of SYNCS

If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.

If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The LPC47B27x has protection

mechanisms to complete the cycle. This is used for EPP data transfers and should utilize the same timeout

protection that is in EPP.

SYNC Error Indication

The LPC47B27x reports errors via the LAD[3:0] = 1010 SYNC encoding.

If the host was reading data from the LPC47B27x, data will still be transferred in the next two nibbles. This data may

be invalid, but it will be transferred by the LPC47B27x. If the host was writing data to the LPC47B27x, the data had

already been transferred.

In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is

transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not

be transferred.

SMSC LPC47B27x

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DATASHEET

Rev. 04-17-07

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