CAM35C44 Ver la hoja de datos (PDF) - SMSC -> Microchip

Número de pieza

componentes Descripción

Lista de partido

CAM35C44

Infrared Communications Controller Chip CameraFR

SMSC -> Microchip 

HPMODE, Bit 0

The HPMODE bit D0 is used to configure the

transceiver type in the CAM35C44 infrared

interface (see FIGURE 6). When HPMODE is

“1” (default), the IRMODE/IRRX3 pin is

configured as an input (IRRX3) to support

transceiver types that require two receive

channels. When HPMODE is “0”, the

IRMODE/IRRX3 pin is configured as an output

(IRMODE) to support transceiver types that

require one receive channel and a mode control

pin.

MIDI, Bit 4

The MIDI bit D4 is the 16C550A UART clock

divider select. When MIDI is “0” (default), the

16C550A clock divider is configured to

generate the standard UART data rates up to

115.2Kbaud.

When MIDI is “1”, the 16C550A clock divider is

configured to generate UART data rates that are

compatible with the 31.25Kbaud ($1%) Musical

Instrument Digital Interface standard.

CR04 - Test Control A

The Test Control A register CR04 enables user-

level serial loopback testing and SMSC internal

test modes.

CR04 can only be accessed in the configuration

state and only after the CSR has been initialized

to 04H. The default value of this register after

power up is 00H (TABLE 19).

TABLE 19 - TEST CONTROL A REGISTER

D7 D6

D5

D4

D3

D2

D1

D0

CR04 R/W

IR_TEST[6:0]

IR_LB

DEFAULT

0x00

IR_LB, Bit 0

The IR_LB bit D0 enables serial loopback

testing, independent of the internal IrCC 2.0

loopback controls. When IR_LB is “1” the

transmit output is internally connected to the

receiver input. When IR_LB is “0” (default), the

transmit output is not connected to the receive

input and loopback testing is disabled.

IR_TEST[6:0], Bits 1 - 7

The IR_TEST[6:0] bits D1 - D7 control SMSC

internal test modes.

SMSC use, only. Activating SMSC internal test

modes may produce undesired results.

CR05 - Software Select A

The Software Select A register CR05 is directly

connected to the read-only IrCC 2.0 Software

Select A register in SCE Register Block Three.

Writing to CR05 is the only way to revise the

contents of the Software Select A register.

CR05 can only be accessed in the configuration

state and only after the CSR has been initialized

to 05H. The default value of this register after

power up is 00H (TABLE 20).

The IR_TEST[6:0] bits are “0” (default) for

normal operation.

When any of the IR_TEST[6:0] bits are “1”, an

SMSC internal test mode is activated. Note:

SMSC internal test modes are reserved for

25

Share Link: