CAM35C44 Ver la hoja de datos (PDF) - SMSC -> Microchip

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CAM35C44

Infrared Communications Controller Chip CameraFR

SMSC -> Microchip 

TABLE 25 - EXAMPLE POWER CONSUMPTION VS. POWER CONTROL ENABLES

POWER

CR08[3:0]

CONSUMPTION

CLOCK

ACE

(ICC)

GENERATO BLOCK

PLL

R

1

SCE

BLOCK2

D3 D2 D1 D0

00 0 0

TYP

1#A4

2#A5

(Note3)

MAX

2.5#A4

5#A5

(Note3)

OFF

OFF

OFF

OFF

0 0 0 1 500#A

1mA

RUNNING

OFF

OFF

OFF

00 1 1

1mA

2mA

RUNNING

ON

OFF

OFF

0 1 1 1 1.6mA

3mA

RUNNING

ON

RUNNING

OFF

11 1 1

6mA

8mA

RUNNING

ON

RUNNING

ON

Note1:

Note2:

Note3:

Note4:

Note5:

The 24MHz crystal oscillator directly driving the ACE block enables data transfers up to

115.2Kbps.

The PLL driving the SCE block enables data transfers up to 4Mbps.

PWRGD does not stop the crystal from oscillating if OSC_ON, D0 in configuration register

CR08, is “1”.

PWRGD is “0”.

PWRGD is “1”.

CR09 - Test Control B

The IR_TEST[14:7] bits D0 - D7 in the Test

Control B register enable SMSC internal test

modes. CR09 can only be accessed in the

configuration state and only after the CSR has

been initialized to 09H. The default value of this

register after power up is 00H (TABLE 26). The

IR_TEST[14:7] bits are “0” (default)

for normal operation. When any of the

IR_TEST[14:7] bits are “1”, an SMSC internal

test mode is activated. Note: SMSC internal test

modes are reserved for SMSC use, only.

Activating SMSC internal test modes may

produce undesired results.

CR09 R/W

TABLE 26 - TEST CONTROL B REGISTER

D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT

IR_TEST[14:7]

0x00

29

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