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CAM35C44

Infrared Communications Controller Chip CameraFR

SMSC -> Microchip 

DESCRIPTION OF PIN FUNCTIONS

NAME

TABLE 1 - CAM35C44 PIN FUNCTION DESCRIPTION

TOTAL

PINS

SYMBOL

BUFFER

TYPE

DESCRIPTION

PROCESSOR/HOST INTERFACE (25)

ISA System Data Bus/

Multiplexed

Address/Data Bus

(Non-ISA)

8 SD[7:0]/AD[7:0]

IO12

This 8 bit bus is used to exchange

data with the host. The bus is bi-

directional and can be configured

as either an ISA system data bus

or as a multiplexed address/data

bus (TABLE 3). These pins are in

a high-impedance state when not

in the output mode.

ISA System Address

Bus (SA0 - SA1)/

General Purpose I/O

(GPIO3 - GPIO4)4

2 SA[1:0]/GPIO[4:3] I/IO12 The ISA system address bus is

used to determine the I/O address

during read and write cycles.

These two ISA system address

bus pins are general purpose I/O

pins (TABLE 30) when a

multiplexed address/data host

interface type is selected (TABLE

3).

ISA System Address

Bus (SA2 - SA4)/

Memory Block Selects

(BS0 - BS2)

3 SA[4:2]/BS[2:0]

I

The ISA system address bus is

used to determine the I/O address

during read and write cycles.

These three ISA system address

bus pins are memory block select

pins (TABLE 10) when a

multiplexed address/data host

interface type is selected (TABLE

3).

Chip Select

1 nCS

I

The active low chip select input is

a 32-byte address block decoder

when the ISA host interface type

is selected and a 256-byte page

decoder when a multiplexed

address/data host interface type is

selected (TABLE 3).

6

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