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CDB6420

Full-Duplex Speakerphone Chip

Cirrus Logic 

CS6420

Threshold

The sensitivity of the speech detector controls

channel switching and ownership in half-duplex

mode. The transmit speech detector registers

speech if the transmit channel signal power is TH-

Det above the noise floor of the transmit channel.

TSAtt - Transmit Suppression Attenuation

This parameter sets the amount of suppression at-

tenuation inserted into the transmit path when

transmit suppression is engaged.

TSBias - Transmit Suppression Bias

The bias level affects the ease with which near-end

speech may break-in or be crushed by far-end

speech. See the Design Considerations section on

Transmit Suppression for full details.

TSThd - Transmit Suppression Threshold

This parameter sets the ERLE requirement for dis-

crimination between echo and near-end speech by

the supplementary echo suppressor. See the De-

sign Considerations section on Transmit Suppres-

sion for full details.

HHold - Hold in Half-Duplex on Howl

This is a control flag which, if enabled, holds the

system in the half-duplex operation if it were to

howl for any reason and the howl detectors trip and

clear coefficients. The system may transition to

full-duplex if the flag is subsequently cleared.

Reset

A hardware reset, achieved by bringing RST low

for at least 1 µs and then high again, must be ap-

plied after initial power-on.

When RST is held low, the various internal blocks

of the CS6420 are powered down. When RST is

brought high, the oscillator is enabled and approx-

imately 4 ms later, all digital clocks begin operat-

ing. The ADCs and DACs are calibrated and all

internal digital initializations occur. The MCR is

sampled after the reset timer expires (104 ms after

the rise of RST or sooner if using the early exit de-

scribed below) to determine whether the reset was

warm or cold. After the MCR is initially sampled,

the default (reset) values of the MCR are restored

to it.

Cold reset is a total reset of all the components of

the CS6420. The ADCs and DACs are reset, the

echo canceller memories and registers are all

cleared, and the default settings of the MCR are re-

stored. Cold reset is the default reset mode upon

power up or in the absence of a microcontroller.

Warm reset is like cold reset except that the echo

canceller coefficients and certain key variables are

not cleared, but instead keep their pre-reset value.

This gives the CS6420 a headstart in adapting to its

environment if the echo environment is relatively

stable, assuming a cold reset happened at least once

since power up.

The CS6420 is warm reset by raising the RST pin

high, waiting 4 ms for the digital clocks to start, and

then writing 0111111111111110 (0x7FFE) to the

MCR within 104 ms after RST goes high. If no

control word is sent, the CS6420 will cold reset. If

the control word is sent after the timer has expired,

it is interpreted as a normal control word.

Another special reset option is to exit the 100 ms

reset timer before the 100 ms has elapsed. This is

accomplished by writing a control word to the

MCR with Bit 15 set high. To exit the timer early

in cold reset, write 1000000000000 (0x8000). The

timer may be bypassed and warm reset asserted by

sending 1111111111111110 (0xFFFE). The

100 ms timer prevents operation until the bias volt-

ages generated on-chip settle, but the startup delay

might be objectionable in some applications.

Clocking

The clock for the converters and DSP is provided

via the clocking pins, CLKI (pin 14) and CLKO

(pin 13). A 20.480 MHz parallel resonant crystal

DS205PP2

19

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