CY7C1049DV33-10VXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1049DV33-10VXI Datasheet PDF : 14 Pages
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AC Switching Characteristics
Over the Operating Range [7]
Parameter
Description
Read Cycle
tpower[8]
VCC(typical) to the first access
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[9]
OE HIGH to High Z[9, 10]
CE LOW to Low Z[9]
CE HIGH to High Z[9, 10]
tPU
CE LOW to Power up
tPD
CE HIGH to Power down
Write Cycle[11, 12]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE LOW to Write End
Address Set up to Write End
Address Hold from Write End
Address Set up to Write Start
WE Pulse Width
Data Set up to Write End
Data Hold from Write End
WE HIGH to Low Z[9]
WE LOW to High Z[9, 10]
CY7C1049DV33
-10 (Industrial)
Min
Max
100
–
10
–
–
10
3
–
–
10
–
5
0
–
–
5
3
–
–
5
0
–
–
10
10
–
7
–
7
–
0
–
0
–
7
–
5
–
0
–
3
–
–
5
-12 (Automotive)
Min
Max Unit
100
–
s
12
–
ns
–
12
ns
3
–
ns
–
12
ns
–
6
ns
0
–
ns
–
6
ns
3
–
ns
–
6
ns
0
–
ns
–
12
ns
12
–
ns
8
–
ns
8
–
ns
0
–
ns
0
–
ns
8
–
ns
6
–
ns
0
–
ns
3
–
ns
–
6
ns
Notes
7.
Test conditions assume signal
and 30 pF load capacitance.
transition
time
of
3
ns
or
less,
timing
reference
levels
of
1.5
V,
input
pulse
levels
of
0
to
3.0
V,
and
output
loading
of
the
specified
IOL/IOH
8. tPOWER gives the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access is performed.
9. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 1 on page 5. Transition is measured when the outputs enter a high impedance state.
11. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set up and hold timing must be referred to the leading edge of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05475 Rev. *G
Page 6 of 14
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