CY7C1049DV33-10VXI Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1049DV33-10VXI

4-Mbit (512 K × 8) Static RAM

Cypress Semiconductor 

CY7C1049DV33

Switching Waveforms

Figure 3. Read Cycle No. 1[13, 14]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

Figure 4. Read Cycle No. 2 (OE Controlled)[14, 15]

DATA VALID

ADDRESS

tRC

CE

OE

DATA OUT

SUPVPCLCY

CURRENT

ADDRESS

CE

WE

tACE

tDOE

tLZOE

HIGH IMPEDANCE

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tLZCE

tPU

50%

tPD

ICC

50%

ISB

Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[16, 17]

tWC

tSCE

tAW

tHA

tSA

tPWE

OE

DATA I/O

NOTE 17

tHZOE

tSD

tHD

DATAIN VALID

Notes

13. Device is continuously selected. OE, CE = VIL.

14. WE is HIGH for read cycle.

15. Address valid prior to or coincident with CE transition LOW.

16. Data IO is high impedance if OE = VIH.

17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

Document Number: 38-05475 Rev. *G

Page 7 of 14

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